ADSP-SC583 datasheet(19/173 Pages) AD

19 / 173 page

Rev. B

Page 19 of 173

December 2018

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Watchdog Timer (WDT)

Two on-chip software watchdog timers (WDT) can be used by

the Arm Cortex-A5 and/or SHARC+ cores. A software watch-

dog can improve system availability by forcing the processors to

a known state, via a general-purpose interrupt, or a fault, if the

timer expires before being reset by software.

The programmer initializes the count value of the timer, enables

the appropriate interrupt, then enables the timer. Thereafter,

the software must reload the counter before it counts down to

zero from the programmed value, protecting the system from

remaining in an unknown state where software that normally

resets the timer stops running due to an external noise condi-

tion or software error.

General-Purpose Counters (CNT)

A 32-bit counter (CNT) is provided that can operate in general-

purpose up/down count modes and can sense 2-bit quadrature

or binary codes as typically emitted by industrial drives or man-

ual thumbwheels. Count direction is either controlled by a level-

sensitive input pin or by two edge detectors.

A third counter input can provide flexible zero marker support

and can input the push button signal of thumbwheel devices. All

three CNT0 pins have a programmable debouncing circuit.

Internal signals forwarded to a GP timer enable this timer to

measure the intervals between count events. Boundary registers

enable auto-zero operation or simple system warning by inter-

rupts when programmed count values are exceeded.

PCI Express (PCIe)

A PCI express interface (PCIe) is available on some product

variants (see Table 2 and Table 3). This single, bidirectional lane

can be configured to be either a root complex (RC) or end point

(EP) system. The PCIe interface has the following features:

• Designed to be compliant with the PCI Express Base

Specification 3.0

• Support for transfers at either 2.5 Gbps (Gen 1) or 5.0 Gbps

(Gen 2) in each direction

• Support for 8b/10b encode and decode

• Lane reversal and lane polarity inversion

• Flow control of data in both the transmit and receive

directions

• Support for removal of corrupted packets for error detec-

tion and recovery

• Maximum transaction payload of 256 bytes

Housekeeping Analog-to-Digital Converter (HADC)

The housekeeping analog-to-digital converter (HADC) pro-

vides a general-purpose, multichannel successive

approximation ADC. It supports the following set of features:

• 12-bit ADC core with built in sample-and-hold.

• 8 single-ended input channels that can be extended to 15

channels by adding an external channel multiplexer.

• Throughput rates up to 1 MSPS.

• Single external reference with analog inputs between

0 V and 3.3 V.

• Selectable ADC clock frequency including the ability to

program a prescaler.

• Adaptable conversion type; allows single or continuous

conversion with option of autoscan.

• Autosequencing capability with up to 15 autoconversions

in a single session. Each conversion can be programmed to

select 1 to 15 input channels.

• 16 data registers (individually addressable) to store conver-

sion values.

USB 2.0 On the Go (OTG) Dual-Role Device Controller

There are two USB modules + PHY. USB0 supports HS/FS/LS

USB 2.0 on the go (OTG) and USB1 supports HS/FS USB 2.0

only and can be programmed to be a host or device.

The USB 2.0 OTG dual-role device controller provides a low

cost connectivity solution in industrial applications, as well as

consumer mobile devices such as cell phones, digital still cam-

eras, and MP3 players. The USB 2.0 controller allows these

devices to transfer data using a point to point USB connection

without the need for a PC host. The module can operate in a tra-

ditional USB peripheral only mode as well as the host mode

presented in the OTG supplement to the USB 2.0 specification.

The USB clock is provided through a dedicated external crystal

or crystal oscillator.

The USB OTG dual-role device controller includes a PLL with

programmable multipliers to generate the necessary internal

clocking frequency for the USB.

Media Local Bus (Media LB)

The automotive model has a Media LB (MLB) slave interface

that allows the processors to function as a media local bus

device. It includes support for both 3-pin and 6-pin media local

bus protocols. The MLB 3-pin configuration supports speeds up

to 1024 × FS. The MLB 6-pin configuration supports a speed of

2048 × FS. The MLB also supports up to 64 logical channels

with up to 468 bytes of data per MLB frame.

The MLB interface supports MOST25, MOST50, and MOST150

data rates and operates in slave mode only.

2-Wire Controller Interface (TWI)

The processors include three 2-wire interface (TWI) modules

that provide a simple exchange method of control data between

multiple devices. The TWI module is compatible with the

widely used I2C bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation and

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400 kb/sec. The TWI interface pins are compatible

with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

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