ADSP-SC583 datasheet(14/173 Pages) AD

14 / 173 page

Rev. B

Page 14 of 173

December 2018

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

point), and illegal instructions cause core exceptions. Con-

ditions triggered on the other side by the SEC, such as error

correcting codes (ECC)/parity/watchdog/system clock,

cause system exceptions.

• An interrupts event occurs asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

System Event Controller (SEC)

Both SHARC+ cores feature a system event controller. The SEC

features include the following:

• Comprehensive system event source management includ-

ing interrupt enable, fault enable, priority, core mapping,

and source grouping

• A distributed programming model where each system

event source control and all status fields are independent of

each other

• Determinism where all system events have the same propa-

gation delay and provide unique identification of a specific

system event source

• A slave control port that provides access to all SEC registers

for configuration, status, and interrupt/fault services

• Global locking that supports a register level protection

model to prevent writes to locked registers

• Fault management including fault action configuration,

time out, external indication, and system reset

Trigger Routing Unit (TRU)

The trigger routing unit (TRU) provides system-level sequence

control without core intervention. The TRU maps trigger

masters (generators of triggers) to trigger slaves (receivers of

triggers). Slave endpoints can be configured to respond to trig-

gers in various ways. Common applications enabled by the TRU

include,

• Automatically triggering the start of a DMA sequence after

a sequence from another DMA channel completes

•Software triggering

• Synchronization of concurrent activities

SECURITY FEATURES

The following sections describe the security features of the

ADSP-SC58x/ADSP-2158x processors.

Arm TrustZone

The ADSP-SC58x processors provide TrustZone technology

that is integrated into the Arm Cortex-A5 processors. The

TrustZone technology enables a secure state that is extended

throughout the system fabric.

Cryptographic Hardware Accelerators

The ADSP-SC58x/ADSP-2158x processors support standards-

based hardware accelerated encryption, decryption, authentica-

tion, and true random number generation.

Support for the hardware-accelerated cryptographic ciphers

includes the following:

• AES in ECB, CBC, ICM, and CTR modes with 128-bit,

192-bit, and 256-bit keys

• DES in ECB and CBC mode with 56-bit key

• 3DES in ECB and CBC mode with 3x 56-bit key

• ARC4 in stateful, stateless mode, up to 128-bit key

Support for the hardware accelerated hash functions includes

the following:

•SHA-1

• SHA-2 with 224-bit and 256-bit digests

• HMAC transforms for SHA-1 and SHA-2

•MD5

Public key accelerator (PKA) is available to offload computation

intensive public key cryptography operations.

Both a hardware-based nondeterministic random number gen-

erator and pseudorandom number generator are available.

Secure boot is also available with 224-bit elliptic curve digital

signatures ensuring integrity and authenticity of the boot

stream. Optionally, ensuring confidentiality through AES-128

encryption is available.

Employ secure debug to allow only trusted users to access the

system with debug tools.

System Protection Unit (SPU)

The system protection unit (SPU) guards against accidental or

unwanted access to an MMR space of the peripheral by provid-

ing a write protection mechanism. The user can choose and

configure the protected peripherals as well as configure which of

the four system MMR masters (two SHARC+ cores, memory

DMA, and CoreSight debug) the peripherals are guarded

against.

The SPU is also part of the security infrastructure. Along with

providing write protection functionality, the SPU is employed

to define which resources in the system are secure or nonsecure

and to block access to secure resources from nonsecure masters.

CAUTION

This product includes security features that can be

used to protect embedded nonvolatile memory

contents and prevent execution of unauthorized

code. When security is enabled on this device

(either by the ordering party or the subsequent

receiving parties), the ability of Analog Devices to

conduct failure analysis on returned devices is

limited. Contact Analog Devices for details on the

failure analysis limitations for this device.

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