ADSP-SC583 datasheet(97/173 Pages) AD

97 / 173 page

Rev. B

Page 97 of 173

December 2018

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Asynchronous Flash Write

Table 51 and Figure 17 show asynchronous flash memory write timing, related to the SMC.

All Accesses

Table 52 describes timing that applies to all memory accesses, related to the SMC.

Table 51. Asynchronous Flash Write

Parameter

Min

Max

Unit

Switching Characteristics

tAMSADV

SMC0_Ax/SMC0_AMSx Assertion Before ADV Low1

1 PREST value set using the SMC_BxETIM.PREST bits.

PREST × tSCLK0 – 2

tDADVAWE

SMC0_AWE Low Delay From ADV High2

2 PREAT value set using the SMC_BxETIM.PREAT bits.

PREAT × tSCLK0 – 2

tWADV

NR_ADV Active Low Width3

3 WST value set using the SMC_BxTIM.WST bits.

WST × tSCLK0 – 2

tHAWE

Output4 Hold After SMC0_AWE High5

4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.

5 WHT value set using the SMC_BxTIM.WHT bits.

WHT × tSCLK0 – 3.5

tWAWE

6 SMC_BxCTL.ARDYEN bit = 0.

SMC0_AWE Active Low Width7

7 WAT value set using the SMC_BxTIM.WAT bits.

WAT × tSCLK0 – 2

Figure 17. Asynchronous Flash Write

Table 52. All Accesses

Parameter

Min

Max

Unit

Switching Characteristic

tTURN

SMC0_AMSx Inactive Width

(IT + TT) × tSCLK0 – 2

NOR_CE

(SMC0_AMSx)

NOR_WE

(

SMC0_AWE)

NOR_A 25-1

(SMC0_Ax)

NOR_ADV

(SMC0_AOE)

tAMSADV

tDADVAWE

NOR_DQ 15-0

(SMC0_Dx)

tWADV

tWAWE

tHAWE

ADSP-SC583 Datasheet(PDF) 97 Page - Analog Devices

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