ADSP-SC583 datasheet(27/173 Pages) AD

27 / 173 page

Rev. B

Page 27 of 173

December 2018

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

DMC_UDQS

InOut

Data Strobe for Upper Byte (Complement). Complement of UDQS. Not used in single-ended mode.

DMC_VREF

Input

Voltage Reference. Externally driven to VDD_DMC/2. Applies to DMC0_VREF and DMC1_VREF pins.

DMC_WE

Output

Write Enable. Defines the operation for external dynamic memory to perform in conjunction with

other DMC command signals. Connect to the WE input of dynamic memory.

ETH_CRS

Input

Carrier Sense/RMII Receive Data Valid. Multiplexed on alternate clock cycles.

CRS— asserted by the PHY when either the transmit or receive medium is not idle. Deasserted when

both are idle.

RXDV—asserted by the PHY when the data on RXDn is valid.

ETH_MDC

Output

Management Channel Clock. Clocks the MDC input of the PHY for RMII/RGMII.

ETH_MDIO

InOut

Management Channel Serial Data. Bidirectional data bus for PHY control for RMII/RGMII.

ETH_PTPAUXIN[n]

Input

PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it

in the auxiliary time stamp FIFO.

ETH_PTPCLKIN[n]

Input

PTP Clock Input. Optional external PTP clock input.

ETH_PTPPPS[n]

Output

PTP Pulse Per Second Output. When the advanced time stamp feature enables, this signal is asserted

based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter is

incremented.

ETH_REFCLK

Input

Reference Clock. Externally supplied Ethernet clock.

ETH_RXCLK_REFCLK

Input

RXCLK (10/100/1000) or REFCLK (10/100).

ETH_RXCTL_CRS

Input

RXCTL (10/100/1000) or CRS (10/100).

ETH_RXD[n]

Input

Receive Data n. Receive data bus.

ETH_TXCLK

Output

Transmit Clock.

ETH_TXCTL_TXEN

Output

TXCTL (10/100/1000) or TXEN (10/100).

ETH_TXD[n]

Output

Transmit Data n. Transmits data bus.

ETH_TXEN

Output

Transmit Enable. When asserted, signal indicates the data on TXDn is valid.

HADC_EOC_DOUT

Output

End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the

end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate

bit in HADC_CTL.

HADC_MUX[n]

Input

Controls to External Multiplexer. Allows additional input channels when connected to an external

multiplexer.

HADC_VIN[n]

Input

Analog Input at Channel n. Analog voltage inputs for digital conversion.

HADC_VREFN

Input

Ground Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

HADC_VREFP

Input

External Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

JTG_TCK

Input

JTAG Clock. JTAG test access port clock.

JTG_TDI

Input

JTAG Serial Data In. JTAG test access port data input.

JTG_TDO

Output

JTAG Serial Data Out. JTAG test access port data output.

JTG_TMS

Input

JTAG Mode Select. JTAG test access port mode select.

JTG_TRST

Input

JTAG Reset. JTAG test access port reset.

LP_ACK

InOut

Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output.

When the link port is configured as a transmitter, ACK is an input.

LP_CLK

InOut

Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured

as a transmitter, CLK is an output.

LP_D[n]

InOut

Data n. Data bus. Input when receiving, output when transmitting.

MLB_CLKN

Input

Differential Clock (–).

MLB_CLKP

Input

Differential Clock (+).

MLB_DATN

InOut

Differential Data (–).

MLB_DATP

InOut

Differential Data (+).

MLB_SIGN

InOut

Differential Signal (–).

Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)

Signal Name

Direction

Description

ADSP-SC583 Datasheet(PDF) 27 Page - Analog Devices

ADSP-SC583 Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL