VT8235 datasheet(16/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-10-

Pin Descriptions

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CPU Interface

Signal Name

Pin # I/O Signal Description

A20M#

T25

OD A20 Mask. Connect to A20 mask input of the CPU to control address bit-20 generation.

Logical combination of the A20GATE input (from internal or external keyboard controller)

and Port 92 bit-1 (Fast_A20).

FERR#

U26

Numerical Coprocessor Error.

This signal is tied to the coprocessor error signal on the

CPU. Internally generates interrupt 13 if active. Output voltage swing is programmable tot

1.5V or 2.5V by Device 17 Function 0 Rx67[2].

IGNNE#

T26

OD Ignore Numeric Error. This pin is connected to the CPU “ignore error” pin.

INIT#

R25

OD Initialization. The VT8235 asserts INIT# if it detects a shut-down special cycle on the PCI

bus or if a soft reset is initiated by the register

INTR

T23

OD CPU Interrupt. INTR is driven by the VT8235 to signal the CPU that an interrupt request

is pending and needs service.

NMI

R23

OD Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The

VT8235 generates an NMI when PCI bus SERR# is asserted.

SLP#

U25

OD Sleep. Used to put the CPU to sleep.

SMI#

T24

OD System Management Interrupt. SMI# is asserted by the VT8235 to the CPU in response

to different Power-Management events.

STPCLK#

R26

OD Stop Clock. STPCLK# is asserted by the VT8235 to the CPU to throttle the processor

clock.

Note: Connect each of the above signals to 150

Ω pullup resistors to VCC_CMOS (see Design Guide).

CPU Speed Control Interface

Signal Name

Pin # I/O Signal Description

VGATE

/ GPIO8

/ PCREQA

Voltage Gate.

Signal from the CPU voltage regulator. High indicates the voltage regulator

output is stable. This pin performs the VGATE function if Device 17 Function 0 Rx53[7] =

0, E5[4] = 1 and E4[3] = 0.

VIDSEL

/ GPIO28

P25

OD Voltage Regulator ID Select. Connected to the CPU voltage regulator. Low selects the

voltage ID from the CPU; high selects a different fixed voltage ID (the lower voltage used

for CPU deep sleep mode). This pin performs the VIDSEL function if Func 0 RxE5[3] = 0.

VRDSLP

/ GPIO29

P24

OD Voltage Regulator Deep Sleep.

Connected to the CPU voltage regulator. High selects

the proper voltage for deep sleep mode.

This pin performs the VRDPSLP function if

Function 0 RxE5[3] = 0.

GHI#

/ GPIO22

R24

OD CPU Speed Select. Connected to the CPU voltage regulator, used to select high speed (L)

or low speed (H). This pin performs the GHI# function if Function 0 RxE5[3] = 0.

DPSLP#

/ GPIO23

P26

OD CPU Deep Sleep.

CPUMISS

/ GPI17

CPU Missing.

Used to detect the physical presence of the CPU chip in its socket. High

indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of

this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and

GPI17 at the same time.

AGPBZ#

/ GPI6

AGP Busy.

Low indicates that an AGP master cycle is in progress (CPU speed transitions

will be postponed if this input is asserted low). Connected to the AGP Bus AGPBZ# pin.

Summary of Internal Pull-Up / Pull-Down Resistor Implementation

Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0]

Internal Pulldowns are present on pins SA[19-16] and all LAN pins

VT8235 Datasheet(PDF) 16 Page - VIA Technologies, Inc.

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