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VT8235 Datasheet(PDF) 80 Page - VIA Technologies, Inc.

Part # VT8235
Description  V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE
PDF  145 Pages
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Manufacturer  VIA [VIA Technologies, Inc.]
Direct Link  https://www.viatech.com/en/
Logo VIA - VIA Technologies, Inc.

VT8235 Datasheet(HTML) 80 Page - VIA Technologies, Inc.

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VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002
-74-
Device 17 Function 0 Power Management Registers
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Offset 85-84 - Primary Interrupt Channel (0000h) ........RW
If a device IRQ is enabled as a Primary IRQ, that device’s
IRQ can be used to generate wake events. The bits in this
register are used in conjunction with:
PMIO Rx28[7] – Primary Resume Status
PMIO Rx2A[7] – Primary Resume Enable
If a device on one of the IRQ’s is set to enable the Primary
Interrupt, once the device generates an IRQ, the PMIO
Rx28[7] status bit will become 1 to report the occurrence of
the Primary IRQ.
If PMIO Rx2A[7] is set to 1 to enable
Resume-on-Primary-IRQ, the IRQ then becomes a wake
event.
15
1/0 = Ena/Disa IRQ15 as Primary Intrpt Channel
14
1/0 = Ena/Disa IRQ14 as Primary Intrpt Channel
13
1/0 = Ena/Disa IRQ13 as Primary Intrpt Channel
12
1/0 = Ena/Disa IRQ12 as Primary Intrpt Channel
11
1/0 = Ena/Disa IRQ11 as Primary Intrpt Channel
10
1/0 = Ena/Disa IRQ10 as Primary Intrpt Channel
9
1/0 = Ena/Disa IRQ9 as Primary Intrpt Channel
8
1/0 = Ena/Disa IRQ8 as Primary Intrpt Channel
7
1/0 = Ena/Disa IRQ7 as Primary Intrpt Channel
6
1/0 = Ena/Disa IRQ6 as Primary Intrpt Channel
5
1/0 = Ena/Disa IRQ5 as Primary Intrpt Channel
4
1/0 = Ena/Disa IRQ4 as Primary Intrpt Channel
3
1/0 = Ena/Disa IRQ3 as Primary Intrpt Channel
2
Reserved
........................................ always reads 0
1
1/0 = Ena/Disa IRQ1 as Primary Intrpt Channel
0
1/0 = Ena/Disa IRQ0 as Primary Intrpt Channel
Offset 87-86 - Secondary Interrupt Channel (0000h) .... RW
For legacy PMU, the bits in this register are used in
conjunction with:
PMIO Rx28[1] – Secondary Event Timer Timeout Status
PMIO Rx2A[7] – SMI on Secondary Event Timer Timeout
Secondary IRQ’s are different from Primary IRQ’s in that
systems that resume due to a Secondary IRQ can return
directly to suspend state after the secondary event timer times
out. For this to work, PMIO Rx2A[1] needs to be set to one to
enable SMI-on-Secondary-Event-Timer-Timeout (when PMIO
Rx28[1] = 1). The timer’s count value can be set via Rx93-
90[27-26].
15
1/0 = Ena/Disa IRQ15 as Secondary Intr Channel
14
1/0 = Ena/Disa IRQ14 as Secondary Intr Channel
13
1/0 = Ena/Disa IRQ13 as Secondary Intr Channel
12
1/0 = Ena/Disa IRQ12 as Secondary Intr Channel
11
1/0 = Ena/Disa IRQ11 as Secondary Intr Channel
10
1/0 = Ena/Disa IRQ10 as Secondary Intr Channel
9
1/0 = Ena/Disa IRQ9 as Secondary Intr Channel
8
1/0 = Ena/Disa IRQ8 as Secondary Intr Channel
7
1/0 = Ena/Disa IRQ7 as Secondary Intr Channel
6
1/0 = Ena/Disa IRQ6 as Secondary Intr Channel
5
1/0 = Ena/Disa IRQ5 as Secondary Intr Channel
4
1/0 = Ena/Disa IRQ4 as Secondary Intr Channel
3
1/0 = Ena/Disa IRQ3 as Secondary Intr Channel
2
Reserved
........................................always reads 0
1
1/0 = Ena/Disa IRQ1 as Secondary Intr Channel
0
1/0 = Ena/Disa IRQ0 as Secondary Intr Channel



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