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VT8235 Datasheet(PDF) 90 Page - VIA Technologies, Inc. |
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VT8235 Datasheet(HTML) 90 Page - VIA Technologies, Inc. |
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90 / 145 page  VT8235 V-Link South Bridge Revision 1.22 October 24, 2002 -84- I/O Space Power Management Registers UrpuytvrÃDp XrÃ8rp General Purpose Power Management Registers I/O Offset 21-20 - General Purpose Status ...................RWC 15 North Bridge SERR# Status 14 USB Wake-Up Status For STR / STD / Soff 13 AC97 Wake-Up Status Can be set only in suspend mode 12 Battery Low Status Set when the BATLOW# input is asserted low. 11 Notebook Lid Status Set when the LID input detects the edge selected by Rx2C bit-7 (0=rising, 1=falling). 10 Thermal Detect Status Set when the THRM# input detects the edge selected by Rx2C bit-6 (0=rising, 1=falling). 9 Reserved ........................................ always reads 0 8 Ring Status Set when the RING# input is asserted low. 7 Reserved ........................................ always reads 0 6 INTRUDER# Status Set when the INTRUDER# pin is asserted low. 5 PME# Status Set when the PME# pin is asserted low. 4 EXTSMI# Status Set when the EXTSMI# pin is asserted low. 3 Internal LAN PME Status Set when the internal LAN PME signal is asserted. 2 Internal KBC PME Status Set when the internal KBC PME signal is asserted. 1 GPI1 Status Set when the GPI1 pin is asserted low. 0 GPI0 Status Set when the GPI0 pin is asserted low. Note that the above bits correspond one for one with the bits of the General Purpose SCI Enable and General Purpose SMI Enable registers at offsets 22 and 24: an SCI or SMI is generated if the corresponding bit of the General Purpose SCI or SMI Enable registers, respectively, is set to one. The above bits are set by hardware only and can only be cleared by writing a one to the desired bit. I/O Offset 23-22 - General Purpose SCI Enable ............ RW 15 Enable SCI on setting of Rx21-20[15] .............def=0 14 Enable SCI on setting of Rx21-20[14] .............def=0 13 Enable SCI on setting of Rx21-20[13] .............def=0 12 Enable SCI on setting of Rx21-20[12] .............def=0 11 Enable SCI on setting of Rx21-20[11] .............def=0 10 Enable SCI on setting of Rx21-20[10] .............def=0 9 Reserved ........................................always reads 0 8 Enable SCI on setting of Rx21-20[8] ...............def=0 7 Reserved ........................................always reads 0 6 Enable SCI on setting of Rx21-20[6] ...............def=0 5 Enable SCI on setting of Rx21-20[5] ...............def=0 4 Enable SCI on setting of Rx21-20[4] ...............def=0 3 Enable SCI on setting of Rx21-20[3] ...............def=0 2 Enable SCI on setting of Rx21-20[2] ...............def=0 1 Enable SCI on setting of Rx21-20[1] ...............def=0 0 Enable SCI on setting of Rx21-20[0] ...............def=0 These bits allow generation of an SCI using a separate set of conditions from those used for generating an SMI. I/O Offset 25-24 - General Purpose SMI Enable ........... RW 15 Enable SMI on setting of Rx21-20[15] ............def=0 14 Enable SMI on setting of Rx21-20[14] ............def=0 13 Enable SMI on setting of Rx21-20[13] ............def=0 12 Enable SMI on setting of Rx21-20[12] ............def=0 11 Enable SMI on setting of Rx21-20[11] ............def=0 10 Enable SMI on setting of Rx21-20[10] ............def=0 9 Reserved ........................................always reads 0 8 Enable SMI on setting of Rx21-20[8] ..............def=0 7 Reserved ........................................always reads 0 6 Enable SMI on setting of Rx21-20[6] ..............def=0 5 Enable SMI on setting of Rx21-20[5] ..............def=0 4 Enable SMI on setting of Rx21-20[4] ..............def=0 3 Enable SMI on setting of Rx21-20[3] ..............def=0 2 Enable SMI on setting of Rx21-20[2] ..............def=0 1 Enable SMI on setting of Rx21-20[1] ..............def=0 0 Enable SMI on setting of Rx21-20[0] ..............def=0 These bits allow generation of an SMI using a separate set of conditions from those used for generating an SCI. |
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