VT8235 datasheet(88/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-82-

I/O Space Power Management Registers

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I/O Offset 5-4 - Power Management Control..................RW

Soft Resume

This bit is used to allow a system using an AT power

supply to operate as if an ATX power supply were

being used.

Refer to the BIOS Porting Guide for

implementation details.

Disable .................................................. default

Enable

Reserved

........................................ always reads 0

Sleep Enable

................................. Write 1 to activate

This is a write-only bit; reads from this bit always

return zero.

Writing a one to this bit causes the

system to sequence into the sleep (suspend) state

defined by the Sleep Type field.

12-10 Sleep Type

000 Normal On

001 Suspend to RAM (STR)

010 Suspend to Disk (STD) (also called Soft Off).

The VCC power plane is turned off while the

VSUS33 and VBAT planes remain on.

011 Reserved

100 Power On Suspend without Reset

101 Power On Suspend with CPU Reset

110 Power On Suspend with CPU/PCI Reset

111 Reserved

In any sleep state, there is minimal interface between

powered and non-powered planes so that the effort

for hardware design may be well managed.

Reserved

........................................ always reads 0

STD Command Generates System Reset Only

Disable .................................................. default

Enable (STD command generates a system

reset and not STD)

7-3

Reserved

........................................ always reads 0

Global Release

................................. WO, default = 0

This bit is set by ACPI software to indicate the

release of the SCI / SMI lock. Upon setting of this

bit, the hardware automatically sets the BIOS Status

bit. The bit is cleared by hardware when the BIOS

Status bit is cleared by software. Note that the setting

of this bit will cause an SMI to be generated if the

BIOS Enable bit is set (bit-5 of the Global Enable

Bus Master Reload

This bit controls whether bus master requests (PMIO

Rx00[4] = 1) transition the processor from C3 to C0

state.

Bus master requests are ignored by power

management logic ................................. default

Bus master requests transition the processor

from the C3 state to the C0 state

SCI / SMI Select

This bit controls whether SCI or SMI is generated for

power management events triggered by the Power

Button, Sleep Button, and RTC (when PMIO Rx1-0

bits 8, 9, or 10 equal one).

Generate SMI......................................... default

Generate SCI

Note that certain power management events can be

programmed individually to generate an SCI or SMI

independent of the setting of this bit (refer to the

General Purpose SCI Enable and General Purpose

SMI Enable registers at offsets 22 and 24).

Also,

Timer Status & Global Status always generate SCI

and BIOS Status always generates SMI.

I/O Offset 0B-08 - Power Management Timer ............... RW

31-24 Extended Timer Value

This field reads back 0 if the 24-bit timer option is

selected (Rx41 bit-3).

23-0 Timer Value

This read-only field returns the running count of the

power management timer. This is a 24/32-bit counter

that runs off a 3.579545 MHz clock, and counts while

in the S0 (working) system state. The timer is reset

to an initial value of zero during a reset, and then

continues counting until the 14.31818 MHz input to

the chip is stopped. If the clock is restarted without a

reset, then the counter will continue counting from

where it stopped.

VT8235 Datasheet(PDF) 88 Page - VIA Technologies, Inc.

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