VT8235 datasheet(94/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-88-

I/O Space Power Management Registers

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I/O Offset 3B-38 - GP Timer Reload Enable ..................RW

All bits in this register default to 0 on power up.

31-8 Reserved

........................................ always reads 0

GP1 Timer Reload on KBC Access

Normal GP1 Timer Operation ............... default

Setting of KBC_STS causes the GP1 timer to

reload.

GP1 Timer Reload on Serial Port Access

Normal GP1 Timer Operation .............. default

Setting of COMA_STS or COMB_STS causes

the GP1 timer to reload.

Reserved

........................................ always reads 0

GP1 Timer Reload on VGA Access

Normal GP1 Timer Operation .............. default

Setting of VGA_STS causes the GP1 timer to

reload.

GP1 Timer Reload on IDE/Floppy Access

Normal GP1 Timer Operation .............. default

Setting

FDC_STS,

SIDE_STS,

PIDE_STS causes the GP1 timer to reload.

GP3 Timer Reload on GPIO Range 1 Access

Normal GP3 Timer Operation .............. default

Setting of GR1_STS causes the GP3 timer to

reload.

GP2 Timer Reload on GPIO Range 0 Access

Normal GP2 Timer Operation .............. default

Setting of GR0_STS causes the GP2 timer to

reload.

GP0 Timer Reload on Primary Activity

Normal GP0 Timer Operation .............. default

Setting of PACT_STS causes the GP0 timer to

reload. Primary activities are enabled via the

Primary Activity Detect Enable register (offset

37-34) with status recorded in the Primary

Activity Detect Status register (offset 33-30).

I/O Offset 40 – Extended I/O Trap Status ................... RWC

7-5

Reserved

........................................always reads 0

BIOS Write Access Status

GP3 Timer Second Timeout With No Cycles

Disable ................................................... default

Enable (GP3 timer timed out twice with no

cycles in between)

GP3 Timer Second Timeout Status

GPIO Range 3 Access Status

GPIO Range 2 Access Status

I/O Offset 42 – Extended I/O Trap Enable..................... RW

7-5

Reserved

........................................always reads 0

SMI on BIOS Write Access

This bit controls whether SMI is generated when

BIOS Write Access Status Rx40[4] = 1.

Disable ................................................... default

Enable (can be reset only by OCI_Reset)

Reserved

........................................always reads 0

GP3 Timer Second Timeout Reboot

This bit controls whether the system is rebooted

when the GP3 timer times out twice (Rx40[2] = 1).

Disable ................................................... default

Enable

SMI on GPIO Range 3 Access

This bit controls whether SMI is generated when

GPIO range 3 is accessed (Rx40[1] = 1)

Disable ................................................... default

Enable

SMI on GPIO Range 2 Access

This bit controls whether SMI is generated when

GPIO range 2 is accessed (Rx40[0] = 1)

Disable ................................................... default

Enable

VT8235 Datasheet(PDF) 94 Page - VIA Technologies, Inc.

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