VT8235 datasheet(96/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-90-

I/O Space System Management Bus Registers

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System Management Bus I/O-Space Registers

The base address for these registers is defined in RxD1-D0 of

the Device 17 Function 0 PCI configuration registers. The

System Management Bus I/O space is enabled for access by

the system if Device 17 Function 0 RxD2[0] = 1.

I/O Offset 00 – SMBus Host Status...............................RWC

Reserved

........................................ always reads 0

SMB Semaphore...............................................RWC

This bit is used as a semaphore among various

independent software threads that may need to use

the Host SMBus logic and has no effect on hardware.

After reset, this bit reads 0.

Writing 1 to this bit

causes the next read to return 0, then all reads after

that return 1.

Writing 0 to this bit has no effect.

Software can therefore write 1 to request control and

if readback is 0 then it will own usage of the host

controller.

Reserved

........................................ always reads 0

Failed Bus Transaction ....................................RWC

SMBus interrupt not caused by failed bus

transaction ............................................. default

SMBus

interrupt

caused

failed

bus

transaction.

This bit may be set when the

KILL bit (I/O Rx02[1]) is set and can be

cleared by writing a 1 to this bit position.

Bus Collision .....................................................RWC

SMBus interrupt not caused by transaction

collision ................................................. default

SMBus

interrupt

caused

transaction

collision. This bit is only set by hardware and

can be cleared by writing a 1 to this bit

position.

Device Error .....................................................RWC

SMBus interrupt not caused by generation of

an SMBus transaction error................... default

SMBus interrupt caused by generation of an

SMBus transaction error (illegal command

field, unclaimed host-initiated cycle, or host

device timeout).

This bit is only set by

hardware and can be cleared by writing a 1 to

this bit position.

SMBus Interrupt ..............................................RWC

SMBus interrupt not caused by host command

completion............................................. default

SMBus interrupt caused by host command

completion. This bit is only set by hardware

and can be cleared by writing a 1 to this bit

position.

Host Busy

......................................................... RO

SMBus

controller

host

interface

not

processing a command .......................... default

SMBus host controller is busy processing a

command. None of the other SMBus registers

should be accessed if this bit is set.

I/O Offset 01h – SMBus Slave Status........................... RWC

7-6

Reserved

........................................always reads 0

Alert Status ..................................................... RWC

SMBus interrupt not caused by SMBALERT#

signal .................................................... default

SMBus interrupt caused by SMBALERT#

signal. This bit will be set only if the Alert

Enable bit is set in the SMBus Slave Control

set by hardware and can be cleared by writing

a 1 to this bit position.

Shadow 2 Status............................................... RWC

SMBus interrupt not caused by address match

to SMBus Shadow Address Port 2......... default

SMBus interrupt or resume event caused by

slave cycle address match to SMBus Shadow

Address Port 2.

This bit is only set by

hardware and can be cleared by writing a 1 to

this bit position.

Shadow 1 Status............................................... RWC

SMBus interrupt not caused by address match

to SMBus Shadow Address Port 1......... default

SMBus interrupt or resume event caused by

slave cycle address match to SMBus Shadow

Address Port 1.

This bit is only set by

hardware and can be cleared by writing a 1 to

this bit position.

Slave Status ..................................................... RWC

SMBus interrupt not caused by slave event

match .................................................... default

SMBus interrupt or resume event caused by

slave cycle event match of the SMBus Slave

Command

PCI

Function

Configuration Offset D3h (command match)

and the SMBus Slave Event Register at

SMBus Base + Offset 0Ah (data event match).

This bit is only set by hardware and can be

cleared by writing a 1 to this bit position.

Reserved

........................................always reads 0

Slave Busy

......................................................... RO

SMBus

controller

slave

interface

not

processing data ...................................... default

SMBus controller slave interface is busy

receiving data.

None of the other SMBus

registers should be accessed if this bit is set.

VT8235 Datasheet(PDF) 96 Page - VIA Technologies, Inc.

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