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PM73121 Datasheet(PDF) 121 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 121 Page - PMC-Sierra, Inc |
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121 / 223 page ![]() PMC-Sierra, Inc. PM73121 AAL1gator II PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ Figure 69 shows the timing information for all AAL1gator II-initiated RAM write cycles. Figure 69. RAM Write Cycle Timing Symbol Parameter Signals Min Max Unit Twc Write cycle /MEM_CS Tp-2 ns Twdh Write data hold MEM_DATA Tp-Tch-10 ns Twdsu Write data setup MEM_DATA Tch - 4.3 ns Twh Write hold /MEM_CS, MEM_ADDR, /MEM_WE Tp -Tch -10 ns Twsu Write setup MEM_ADDR, /MEM_CS 1 ns Twp Write pulse width /MEM_WE Tch-1.3 Tch+0.3 ns NOTES: • Tch and Tp are the clock high time and clock period as measured at 1.5 V. See Figure 80 on page 119 and refer to section 8.6 “Board Requirements for the SRAM Interface” on page 174. • Test conditions are: /MEM_WE(0) and /MEM_WE(1) at 15 pF; and MEM_DATA, SP_ DATA_EN, SP_DATA_CLK, SP_DATA_DIR, and /MEM_CS at 30 pF; MEM_ADDR and SP_ADDR_EN at 40 pF. • All outputs are measured at 1.5 V, -40 to 85 °C, 4.75 - 5.25 V. Twh Twc Twsu Twc Twp Twp Twdsu Twdh MEM_ADDR(io) /MEM_CS(o) /MEM_WE(o) MEM_DATA(io) |
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