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PM73121 Datasheet(PDF) 124 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 124 Page - PMC-Sierra, Inc |
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124 / 223 page ![]() PMC-Sierra, Inc. PM73121 AAL1gator II PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ Figure 71. Microprocessor RAM Write Cycle Timing Symbol Parameter Signals Min Max Unit Taa (See note below) Acknowledge assertion after /PROC_ CS or /PROC_WR; whichever comes last /PROC_ACK 5 29 SYS_CLK periods Tasu Address setup to write pulse* MEM_ADDR, /MEM_WE 10 ns Tcea /PROC_CS deassertion to /PROC_ACK deassertion /PROC_ACK 2 15 ns Twd Write pulse delay /MEM_WE 8 25 ns Tdsu Data setup to write pulse off* MEM_DATA 15 ns Tded Data enable delay /SP_DATA_EN 7 25 ns Taed Address enable delay /SP_ADD_EN 5 20 ns Tq Clock-to-output delay SP_DATA_DIR 2 15 ns Tddh Taed Taed Tded Tded Tcea Taa Tq Twd Tdsu Twd Tasu Tah Tdh Tasu17 NON_PROC READ CYCLE PROC WRITE CYCLE RECOVERY CYCLE NON_PROC CYCLE 3 4 5 1, 2 SYS_CLK PROC_ADD PROC_DATA /PROC_CS(i) /PROC_WR(i) ADDR17(i) MEM_ADDR(i) MEM_DATA(io) /MEM_CS(o) /MEM_WE(o) /MEM_OE(o) /PROC_ACK(i) /SP_DATA_EN(o) /SP_ADD_EN(o) SP_DATA_DIR(o) |
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