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PM73121 Datasheet(PDF) 127 Page - PMC-Sierra, Inc |
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PM73121 Datasheet(HTML) 127 Page - PMC-Sierra, Inc |
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127 / 223 page  PMC-Sierra, Inc. PM73121 AAL1gator II PMC-980620 ,VVXH AAL1 SAR Processor Data Sheet QSPQSD@U6S`Ã6I9Ã8PIAD9@IUD6GÃUPÃQH8TD@SS6ÃDI8Ã6I9ÃAPSÃDUTÃ8VTUPH@ST¶ÃDIU@SI6GÃVT@ NOTE: Taa is dependent on the HOLDOFF signal. If HOLDOFF is not asserted when the access begins, Taa will be a maximum of six SYS_CLK periods. If the access occurs immediately after another access, then Taa will be 24 to 30 SYS_CLK periods. Refer to section 6.5.3 “Microprocessor Holdoff Timing” on page 116 for a description of the HOLDOFF activity. 6.5.2.3 Microprocessor Write Command Register Timing Figure 73 on page 112 shows the write command register timing. Writing to the internal com- mand register is not honored if higher priority internal functions request the memory, or if the holdoff from a previous microprocessor transfer has not expired. /PROC_CS and /PROC_WR are double sampled (1 and 2) at the rising edge of SYS_CLK, and at (3) ADDR17 is sampled to distinguish between a command register write and a RAM write. As long as HOLDOFF is not high, /SP_ADD_EN, /SP_DATA_EN, and SP_DATA_DIR are acti- vated at the next clock cycle (3), allowing the microprocessor address and data to pass through the address and data buffer to the AAL1gator II. The /SP_ADD_EN and the /SP_DATA_EN signals are delayed to minimize bus conflicts when the microprocessor access follows an Tq Clock-to-output delay SP_DATA_CLK,/MEM_OE (deactivate) 215 ns Tq Clock-to-output delay /MEM_CS 2 18 ns Tqmoe Clock-to-output delay for activation of /MEM_OE MEM_OE (activate) 2 25 ns Tasu17 Address setup to SYS_CLK ADDR17 2 ns Taed Address enable delay /SP_ADD_EN 5 20 ns Tasu Address setup to SP_DATA_CLK* MEM_ADDR, SP_DATA_CLK 26 ns Tded Data enable delay from /PROC_CS and /PROC_RD /SP_DATA_EN, /PROC_CS, /PROC_RD 2** 15** ns Tcea /PROC_CS deassertion to /PROC_ ACK deassertion /PROC_ACK 2 15 ns Tdsu Data setup to SP_DATA_CLK* MEM_DATA 11 ns Tdh Data hold from SP_DATA_CLK* MEM_DATA, SP_DATA_CLK 3 ns Tcaen SP_DATA_CLK high to /SP_ADD_EN high SP_DATA_CLK, /SP_ADD_EN 0 ns Tah MEM_ADDR hold time from SP_ DATA_CLK* MEM_ADD, SP_DATA_CLK 1 ns Tzsu Z state setup-to-clock MEM_ADDR 3** ns * These parameters are dependent on external components and assume that the requirements from Table 26 on page 195 are met. ** These parameters are typical only. Symbol Parameter Signals Min Max Unit |
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