PM9313 datasheet(82/343 Pages) PMC

82 / 343 page

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM9311/2/3/5 ETT1™ CHIP SET

PMC-2000164

ISSUE 3

ENHANCED TT1™ SWITCH FABRIC

Released

Data Sheet

PMC-Sierra, Inc.

1.7.1

The OOB Bus

The OOB bus is an eight-bit, tri-state, multiplexed address/data bus with separate control and interrupt

signals.

1.7.1.1

OOB Bus Signals

Thirteen signals are used:

NOTE: Active low signals are indicated by “_L”.

All signals are point to point except for the AD bus which is a multipoint bus. In particular,

WAIT_L and the interrupt signals are not open collector/gate drivers.

1.7.1.2

Address Space

The OOB bus provides 31 bits of address - A[30:0]. Of these, bits A[1] and A[0] are always 0 as the bus

does not support 8- or 16-bit accesses: all accesses are 32-bits wide, and must be aligned on quad byte

boundaries.

Table 17.

OOB Control Bus Signals

Signal

Name

Description

Driven by M(aster) or S(lave)

AD[7:0]

8 bit address/data bus.

AD[7] indicates the type of cycle (1 = Write, 0 = Read)

during the first address cycle, and is used for for

address/data during other cycles.

A[6:0] must provide the board select address when

VALID_L is high.

Both.

Addressdrivenbymaster.

Data supplied by master for a

write cycle.

Data supplied by Slave for a

read cycle.

VALID_L

Bus cycle is valid. Active low.

Master.

WAIT_L

Wait. Active low.

Initially asserted to indicate slave will respond.

Then asserted, if necessary, to allow slave extra cycles

to respond to current transaction.

Slave

CLK

Clock.

Clock source.

INT_HI

High priority interrupt

Slave

INT_LO

Low priority interrupt

Slave

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