PM9313 datasheet(19/343 Pages) PMC

19 / 343 page

PM9311/2/3/5 ETT1™ CHIP SET

PMC-2000164

ISSUE 3

ENHANCED TT1™ SWITCH FABRIC

Released

Data Sheet

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PMC-Sierra, Inc.

Functional Description

1.1

OVERVIEW

The ETT1TM Chip Set provides a crossbar-based switch core which is capable of switching cells between

32 ports with each port operating at data rates up to 10 Gbit/s. This section describes the main features of

the switch core and how cells flow through a complete system that is based on the ETT1 Chip Set.

This document often refers to port rates of OC-192c or OC-48c. The ETT1 Chip Set itself operates at a

fixed cell rate of 25M cells per second per port and thus is unaware of the actual data rate of the attached

link. So a switch might be 32 ports of OC-192c, or it could be 32 ports of 10 Gbit/s Ethernet; it is the internal

cell rate that is determined by the ETT1 Chip Set, not the link technology.

1.1.1

ETT1 Switch Core Features

The ETT1 switch core provides the following features:

•

320 Gbit/s aggregate bandwidth - up to 32 ports of 10 Gbit/s bandwidth each

•

Each port can be configured as 4 x OC-48c or 1 x OC-192c

•

Both port configurations support four priorities of best-effort traffic for unicast and multicast data

traffic

•

TDM support for guaranteed bandwidth and zero delay variation with 10 Mbit/s channel resolution

•LCSTM protocol supports a physical separation of switch core and linecards up to 200 feet (70 m)

•

Virtual output queues to eliminate head-of-line blocking on unicast cells

•

Internal speedup to provide near-output-queued performance

•

Cells are transferred using a credit mechanism to avoid cell losses due to buffer overrun

•

In-band management and control via Control Packets

•

Out-of-band management and control via a dedicated CPU interface

•

Optional redundancy of all shared components for fault tolerance

•

Efficient support for multicast with cell replication performed within the switch core

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