PM9313 datasheet(86/343 Pages) PMC

86 / 343 page

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM9311/2/3/5 ETT1™ CHIP SET

PMC-2000164

ISSUE 3

ENHANCED TT1™ SWITCH FABRIC

Released

Data Sheet

PMC-Sierra, Inc.

Figure 34. Write Cycle - No Wait

Addresses are presented during cycles A0-A3. The write data is presented during D0-D3. There is then a

recover cycle during which the target performs the write.

1.7.1.7

A Write Cycle - One Wait

If, during D3, the target decides that it may not be able to complete the write immediately, then it must

assert WAIT_L. It continues to assert WAIT_L until the write is completed or WAIT_L has been asserted for

256 cycles, at which time WAIT_L is de-asserted. (If WAIT_L is asserted for 256 cycles then the master will

consider this to be a bus error).

Figure 35. shows a write cycle with the target forcing a one cycle wait. The target slave asserts WAIT_L

during A3 to indicate that the target is active. The target then de-asserts WAIT_L and re-asserts it during

D3. The master must maintain d7:0 until WAIT_L is de-asserted.

Figure35. WriteCycle- OneWait

1.7.1.8

A Read Cycle - One Wait

A simple 32-bit read. The master drives out a 31-bit address, 8 bits at a time, most significant bits first;

AD[7] is driven low in the first cycle to indicate a read cycle. VALID_L is asserted by the master to indicate

the new cycle. The target slave asserts WAIT_L during A3 to indicate that the target is active. The target

CLK

AD[6:0]

d30:24

d22:16

d14:8

d6:0

a30:24

a22:16

a14:8

a6:0

VALID_L

WAIT_L

AD[7]

d31

d23

d15

W/R

a23

a15

Rec

Idle

board address

address

board

CLK

AD[6:0]

d30:24

d22:16

d14:8

d6:0

a30:24

a22:16

a14:8

a6:0

VALID_L

WAIT_L

AD[7]

d31

d23

d15

W/R

a23

a15

Rec

address

board

address

board

PM9313 Datasheet(PDF) 86 Page - PMC-Sierra, Inc

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