PM9313 datasheet(85/343 Pages) PMC

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PM9311/2/3/5 ETT1™ CHIP SET

PMC-2000164

ISSUE 3

ENHANCED TT1™ SWITCH FABRIC

Released

Data Sheet

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PMC-Sierra, Inc.

The combinations of permissible board addresses and device addresses are shown in Table 19.

NOTE: If the satellite OOB controller needs its own address within the OOB space then it can use

0xPPe (i.e. local device select = 0x00e).

1.7.1.4

Port Board Assignment

The port boards must have unique board select addresses in the range 0 to 31. These addresses identify

the logical port number of a port for LCS purposes. The assignment of port addresses is not random and

must reflect the physical connections made between the port boards and the crossbar boards. For

example, one port board will have connections to port 6 on every Crossbar device and port 6 on every

Scheduler. That port board must then have a board address of 6.

1.7.1.5

Bus Cycles

Two types of bus cycles are supported: write and read. Each type may have any number of wait states

before the cycle completes.

1.7.1.6

A Write Cycle - No Wait

A simple 32-bit write. The master drives out a 31-bit address, 8 bits at a time, most significant bits first;

AD[7] is high to indicate a write operation. VALID_L is asserted by the master to indicate the new cycle.

NOTE: The target slave asserts WAIT_L during the final address cycle to indicate that the target is

active. The target then de-asserts WAIT_L with the first data cycle. The master must

de-assert VALID_L for at least one cycle before re-asserting it for the next cycle.

Whenever VALID_L is de-asserted the master must drive the local board address onto AD[6:0].

Table 19.

Unicast Group Selects

Devices

Address Format (bin)

Address range allocated

EPP on port P (P=0..31)

{00P_PPPP_1111}

0x00f, 0x01f, ... 0x1ff

Dataslice D (D=0..13) on port P (P=0..31)

{00P_PPPP_DDDD}a

a. In the ETT1 reference system design, P_PPPP corresponds to the port number (0-1f hex) and DDDD corresponds to the

Dataslice number (0-d hex)

0x000-0x00d,..0x1f0-0x1fd

Scheduler S (S=0,1)

{100_000S_0000}

0x400 or 0x410

Crossbar C (C=0..31)

{010_CCCC_000C}b

b. In the ETT1 reference system design, the first four bits of the CCCC_000C designation correspond to the crossbar board

number, and the last bit of the CCCC_000C designation specifies which of the two crossbar chips on that board is being

addressed. Note that in the reference design, logical crossbars 0 and 6 are on the board with CCCC=0000, logical cross-

bars 1 and 7 are on the board with CCCC=0001, etc.

0x200, 0x201, 0x210...0x2f1

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