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PM9313 Datasheet(PDF) 97 Page - PMC-Sierra, Inc |
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PM9313 Datasheet(HTML) 97 Page - PMC-Sierra, Inc |
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97 / 343 page ![]() PM9311/2/3/5 ETT1™ CHIP SET PMC-2000164 ISSUE 3 ENHANCED TT1™ SWITCH FABRIC Released Data Sheet PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 93 PMC-Sierra, Inc. specified by considering the various AIB links. The following sections explain these procedures for redundant and non-redundant configurations. 1.9.2 Soft/Transient Errors Intermittent CRC errors between the Dataslice and Crossbar and the Enhanced Port Processor and Scheduler are considered in this section. The corrective action that needs to take place due to these errors are different for non-redundant and redundant configurations. 1.9.2.1 Non-Redundant Configurations Dataslice - Crossbar In a non-redundant Crossbar configuration, CRC errors that occur between the Dataslice and Crossbar imply that part of a cell has been corrupted. In Figure 40, Dataslice 1 and Dataslice 2 are connected to Crossbar 0. If a CRC error occurs from Dataslice 1 to Crossbar- 0 when valid data is to be transferred, then that slice of information for that cell has been corrupted. As a result, Dataslice 2 will receive an invalid cell. Crossbar 0 will indicate to the CPU that a CRC error has occurred. If Dataslice 2 receives a CRC error from Crossbar-0 when valid data is to be transferred, then the cell has been corrupted. Dataslice 2 will indicate to the CPU that a CRC error has occurred. In both of the above, if the corrupted cell did contain cell data (as opposed to being an empty cell) Dataslice 2 will store the corrupted information in its local memory and forward it to the egress linecard. The ETT1 fabric will not make the decision to discard the cell; the linecard must detect the error and discard the cell. The linecard would detect such an error with it’s own payload error detection scheme. If the CRC error occurred in an empty cell then no information is lost. However the occurrence of a CRC error is always indicated to the local CPU via a maskable interrupt. Figure 40. Simple Non-Redundant Crossbar Configuration Dataslice 1 Dataslice 2 Crossbar 0 |
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