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TMPR3916 Datasheet(PDF) 41 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 41 Page - Toshiba Semiconductor |
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41 / 225 page  Chapter 1 The TMPR3916 Preliminary 1-4 1.4 Structure of TMPR3916 and a System Example The following picture shows the block diagram of the TMPR3916: Clock Generator / PLL TX39/H Core CORE 4KB I$ 1KB D$ Memory Controller (MC) DSU SDRAMC MEMC GDC VIEWDAC TXCAN Channel 0 Channel 1 INTC TIMER PIO SEI SCI Channel 0 Channel 1 Channel 2 Channel 3 XTAL1,PLLOFF, CLKEN XTAL2 SYSCLK RESET pcst[2:0] dclk dsa0/tpc dbge sdi/dint dreset test[2:0] EXT[2:0] NMI RXCAN0, RXCAN1 TXCAN0, TXCAN1 ROUT GOUT BOUT HSYNC VSYNC/CSYNC HDISP DOTCLK PIO[15:0] / Digital RGB PIO[29:16] / SCI, SEI RAS CAS WE CKE CS[1:0] DMAC Channel 0 Channel 1 DREQ0 DACK0 HALT CS[5:2] Figure 1.4.1 Block Diagram TMPR3916 |
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