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TMPR3916 Datasheet(PDF) 69 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 69 Page - Toshiba Semiconductor

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Chapter 2 Memory Controller (MC)
Preliminary
2-20
2.6
MEMC Function
Channel functionality is specified by applying special values to Channel Control Registers. They must be
accessed using 32-bit cycles.
2.6.1
Channel Assignment
TMPR3916 contains the total of four multi-purpose memory controller channels.
The following chip-select signals are assigned to these channels:
Chip Enable Signal
Assigned to Channel
CS2
MEMC Channel 2
CS3
MEMC Channel 3
CS4
MEMC Channel 4
CS5
MEMC Channel 5 (Boot Channel)
Channel 5 is a special function channel and is used to boot the microprocessor from external devices
like SRAM, ROM or FLASH memories.
2.6.2
Channel 5 Boot Function
For the system boot procedure, it can be chosen, whether the system shall be booted from a 16 or 32
bit device.
This choice is made by connecting a pull-up or pull-down resistor to the A26/ BOOT16 pin. The
value of this pin is latched once during system startup on the rising edge of the reset signal, when the
EBIF data bus is tri-stated.
Value of A26 / BOOT16 Pin
on Rising Edge of Reset
Boot-function
0
Channel 5 is 32-bits wide at boot time
1
Channel 5 is 16-bits wide at boot time
2.6.3
Operational Modes
We can distinguish two operational modes depending on the types of memory connected to the
channels 2 to 5. These two operational modes lead to two different settings: Flash/SRAM setting and
Page Mode ROM setting.
2.6.3.1
Flash/SRAM setting
The SRAM and Flash memories cannot be accessed in page mode. Therefore some parameters
in the RCCRx (x = 2, 3, 4, 5) control registers assume a particular meaning.
The setting of bits RPM is always 00 (“Not configured for page mode”).
The RPWT is no longer used as a wait state parameter for second and following accesses in
burst mode. In non-page mode RPWT and RWT define together the wait time in the access to the
Flash or SRAM. The RWT represents the lower significant bits of the wait time parameter, while
RPWT represents the most significant bits.



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