TMPR3916 datasheet(98/225 Pages) TOSHIBA

98 / 225 page

Chapter 3 Graphics Display Controller (GDC)

Preliminary

3-19

Vertical Synchronous Pulse Width Register (VSWR)

Bit

2120

1615

Name



VSW



Bit

Name

Function

Reset

Value

R/W

31:21



Wired to zero

20:16

VSW

Specifies the vertical sync signal pulse width using the number of

lines.

0x03

R/W

15:0



Wired to zero

Vertical Display Start Register (VDSR) for layers A/E, B and C

Bit

2221

1615

Name



VDS



Bit

Name

Function

Reset

Value

R/W

31:21



Wired to zero

21:16

VDS

These bits specify the vertical display start position using the number

of lines, starting from the VSYNC* signal falling edge.

0x04

R/W

15:0



Wired to zero

Note:

The lowest value allowed for VDS is 2hex.

Vertical Display Start Register (VDSRD) for layer D

Bit

2625

1615

Name



VDSD



Bit

Name

Function

Reset

Value

R/W

31:26



Wired to zero

25:16

VDSD

These bits specify the vertical display start position using the

number of lines, starting from the VSYNC* signal falling edge.

0x0F6

R/W

15:0



Wired to zero

Note:

The lowest value allowed for VDSD is 2hex.

TMPR3916 Datasheet(PDF) 98 Page - Toshiba Semiconductor

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