TMPR3916 datasheet(100/225 Pages) TOSHIBA

100 / 225 page

Chapter 3 Graphics Display Controller (GDC)

Preliminary

3-21

3.5

Setting Examples

Display characters:

Horizontal synchronous cycle is 64 µsec/line,

Vertical synchronous cycle is 16.678 msec/screen.

If DOTCLK = 3 MHz

⇒

DCKPS = 0x9,

HC = 64 µs

× 3 MHz

= 192 dots,

VC = 16.768 ms

× 1/64 µs = 262 lines.

When displaying a 160-dot

× 225-line (32 dots × 32 lines for layer D) picture out of a 368 × 270-frame,

and the frame buffer is SDRAM, then

SARA=0xA0000000,

(physical: 0x50000000)

SARB=0xA0400000,

(physical: 0x50200000)

SARC=0xA0800000,

(physical: 0x50400000)

SARD=0xA0C00000,

(physical: 0x50600000)

MWRA=0x5C,

MWRB=0x5C,

MWRC=0x2E,

MWRD=0x0A.

Please note that the defined start addresses are logical addresses. The physical start address is defined as

the right shifted logical address and a zero as MSB (see chapter 3.4 ‘Start address register’ Figure 3.4.1).

The following are example register settings while internal synchronization signals HSYNC and VSYNC

are used:

HTN

= 0x05,

HTND

= 0x01,

HDS

= 0x17,

HDE

= 0xB7,

HDSD

= 0x37,

HDED

= 0x57,

= 0xC0,

= 0x106,

HSW

= 0x0F,

VSW

= 0x04,

VDS

= 0x1B,

VDE

= 0xFC,

VDSD

= 0x3B,

VDED

= 0x5B.

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