TMPR3916 datasheet(82/225 Pages) TOSHIBA

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Chapter 3 Graphics Display Controller (GDC)

Preliminary

3-3

3.1.2

Frame Buffer

The TMPR3916 supports SDRAM and SRAM as frame buffer.

The GDC uses separated address generators for each of its four layers A/E, B, C, and D. It can

specify the A/E, B, C, or D layer display data address area by writing the data to the start address

display start register (HDSR) and the horizontal display end register (HDER). The HDSR and HDER

are stored as one value in the horizontal display start end register (HDSER).

HDER - HDSR

SARx

SARx + MWRx

MWRx

frame buffer

st line

SARx

32 bit frame buffer

SARx + MWRx

SARx + N

↔ MWRx

(N+1)

th line

nd line

Figure 3.1.2 Frame Buffer Data

The SARx stores the address of the upper-left corner’s dot belonging to layer x. The MWRx stores

the offset value to be added to the contents of SARx to get the address of the left-most pixel of the

following line. It is not allowed to store the last dot of one line and the first dot of the next line within

one memory word as shown below.

The TMPR3916 dot data structure in the frame buffer is as follows: In map mode these values are

addresses for color palette. In picture mode these values represent the displayed colors.

Data Length Per Dot

Active Level

# Colors

Map mode C/D

4 bits

Layers C, D

Map mode A/B

8 bits

Layers A, B

256

Picture mode

16 bits

Layer E

64K

Accordingly, the data structure for each word is as follows.

Bits

31:28

27:24

23:20

19:16

15:12

11: 8

7:4

3:0

Map mode C/D

Dot 1

Dot 2

Dot 3

Dot 4

Dot 5

Dot 6

Dot 7

Dot 8

Map mode A/B

Dot 1

Dot 2

Dot 3

Dot 4

Picture mode

Dot 1

Dot 2

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