TMPR3916 datasheet(61/225 Pages) TOSHIBA

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Chapter 2 Memory Controller (MC)

Preliminary

2-12

Bit

Name

Function

Reset

Value

R/W

ENA

ENA – Module Enable

1 = Enable Module

0 = Disable Module

If SDRAMC is disabled the state-machine of the SDRAM controller

is suspended and the controller will remain in the idle state. This

also means that connected SDRAMs will not be refreshed and that

their contents will be lost.

The module should never be disabled during its normal operation. It

has to be ensured, that no SDRAM accesses are performed on one

of the G-Busses when the module is disabled.

For example, SDRAMC should never be disabled in a situation,

where read accesses are still performed on the video bus. It is

mandatory to disable the GDC before SDRAMC is being disabled.

Software should also ensure, that the internal write-buffer has been

written to SDRAM memory.

Violations to these rules might result in bus hang-ups.

R/W

PWR

PWR – Power-Up Sequence

Setting this bit will run the power-up sequence for all connected and

enabled memory devices. The power-up sequence is described

more closely in the next chapter. This flag can be read to determine

the end of the power-up procedure. At the end of the power-up

sequence, this bit is automatically cleared by the SDRAM controller

state-machine.

R/W

Base Address Register (DCBA)

Bit

Name

BAX



Bit

Name

BAY



Bit

Name

Function

Reset

Value

R/W

31:22

BAX

Base Address Memory Channel X

This register is used to define the base address for memory channel

X. This address is compared to the upper 10 bits of the physical

G-Bus address.

R/W

21:16



Wired to zero

15:6

BAY

Base Address Memory Channels Y

The same as for the memory channel X.

R/W

5:0



Wired to zero

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