TMPR3916 datasheet(50/225 Pages) TOSHIBA

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Chapter 2 Memory Controller (MC)

Preliminary

2-1

Memory Controller (MC)

This system’s memory controller consists of two modules: the SDRAM Controller (SDRAMC) and MEMC

for other types of memory.

Six multi-purpose memory channels can be administrated: While the channels 0 and 1 are assigned to the

SDRAM controller, the memory controller’s channels are numbered from 2 to 5.

The SDRAM Controller contains the following features:

•

uses memory architecture single-data-rate SDRAM

•

2 memory channels with 32 bit width, 16 bit width connectivity is not supported for SDRAM devices

•

base address, mask, DRAM size & organization configurable for each channel (same physical address

space on both Video and System-Busses)

•

true dual G-Bus connectivity

•

read bursts 4, 8, 16, 32 words,

•

single read accesses, single write accesses

•

different, mixed burst sizes on both busses are possible

•

fair memory arbitration, predictable latency

•

memory arbitrated on a first come first serve basis

•

for the case of a simultaneous transaction request, the prioritized G-Bus can be configured

•

one word write-back buffer to reduce bus utilization during write operations

•

low-power / self-refresh mode supported

•

background refresh during MEMC accesses

•

built-in power-up logic

•

programmable refresh cycle

The MEMC contains the following features:

•

4 separate channels

•

Support for ROM, MASK ROM, PAGE MODE ROM, EPROM, EEPROM, SRAM, and FLASH devices

•

Support for Page-Mode

•

Base Address and size programmable per channel

•

external Acknowledge mode for external ASIC slave device connectivity

•

Data Bus width of 16-bit/32-bit is selectable by channel

•

Supports programmable Setup and Hold Time for Address, Chip Enable, Write Enable Signals

•

Channel 5 supports BOOT options

TMPR3916 Datasheet(PDF) 50 Page - Toshiba Semiconductor

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