Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

TMPR3916 Datasheet(PDF) 93 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 93 Page - Toshiba Semiconductor

Back Button TMPR3916 Datasheet HTML 89Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 90Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 91Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 92Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 93Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 94Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 95Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 96Page - Toshiba Semiconductor TMPR3916 Datasheet HTML 97Page - Toshiba Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 93 / 225 page
background image
Chapter 3 Graphics Display Controller (GDC)
Preliminary
3-14
Display Control Register (DCR)
Bit
3130
292827
262524
Name
BLK
DCK
ADS
LPA
LD
LC
LB
LA
Bit
2322
212019
181716
Name
DCKPS
HV
BUSERR
VSYNC
HSYNC
Bit
1514
131211
10
9
8
Name
Bit
7
6
543
210
Name
LSB
MODE
NSYNC
CSEL
ESYNC
Bit
Name
Function
Reset
Value
R/W
31
BLK
0
Blank screen (analog output)
1
Display frame buffer
Note:
In order to blank the digital outputs the PORT module has to
be set to drive the corresponding PIOs. This can be
achieved by setting the lower bits of the PAMUX register to
logic zero. The data values specified in the corresponding
bits of the PA register are output to the PIOs.
0
R/W
30
DCK
0
Selects external dot clock
1
Selects internal dot clock (divides SYSCLK)
0
R/W
29
Wired to zero.
0R
28
LPA
0
Map mode (layer A, 8 bits per dot)
1
Picture mode (layer E, 16 bits per dot)
0
R/W
27
LD
0
Do not display layer D
1
Displays layer D
0
R/W
26
LC
0
Do not display layer C
1
Displays layer C
0
R/W
25
LB
0
Do not display layer B
1
Displays layer B
0
R/W
24
LA
0
Do not display layer A/E
1
Displays layer A/E
0
R/W
23:20
DCKPS
Dot Clock:
0hex
Not allowed
1hex
1/4 system frequency
2hex
1/6 system frequency
3hex
1/8 system frequency
4hex
1/10 system frequency
5hex
1/12 system frequency
6hex
1/14 system frequency
7hex
1/16 system frequency
8hex
1/18 system frequency
9hex
1/20 system frequency
Ahex
1/22 system frequency
Bhex
1/24 system frequency
Others 1/10 system frequency
These bits are relevant only when DCK = 1.
0x4
R/W
19
HV
0
Interrupt at VSYNC*
1
Interrupt at HSYNC*
0
R/W
18
BUSERR
0
No bus error occurred since last write access to DCR
1
Bus error on video bus during GDC display data transfer
When a bus error occurs on video bus this bit is set to 1. It can only
be reset by a write access to DCR (any value for BUSERR bit).
0
R/W



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com