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TMPR3916 Datasheet(PDF) 85 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 85 Page - Toshiba Semiconductor

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Chapter 3 Graphics Display Controller (GDC)
Preliminary
3-6
3.1.3
Display Control Signal
The GDC block generates and outputs the synchronization signal (HSYNC, VSYNC, and CSYNC).
The display uses non-interlaced scanning.
HSWR
HDSR + 8
HDSR + 9
HDER + 8
HCR
HSYNC*
HDER + 8
VDSR + 1
VDER
blanking area
dot data display area
Figure 3.1.6 Display Timing
The GDC block can select and output a separated synchronization (HSYNC*, VSYNC*) or a
composite synchronization (CSYNC*) signal. The composite CSYNC* is the EX-NOR (exclusive nor)
signal of HSYNC* and VSYNC*.
VSYNC*
HSYNC*
CSYNC*
Figure 3.1.7 CSYNC* Timing
In positive mode the composite CSYNC is the EX-OR (exclusive or) signal of HSYNC and VSYNC.
HSYNC
VSYNC
CSYNC
Figure 3.1.8 CSYNC Timing When HSYNC and VSYNC are in Positive Mode
The DCR bit CSEL enables composite synchronization signal output. The bit NSYNC enables using
synchronization signals in positive mode.
Externally separated synchronization signals can also be used for input. Set using the ESYNC bit of
the DCR.



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