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TMPR3916 Datasheet(PDF) 74 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 74 Page - Toshiba Semiconductor |
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74 / 225 page ![]() Chapter 2 Memory Controller (MC) Preliminary 2-25 ROM Channel Control Register 5 (RCCR5) The channel 5 is used as boot channel. Note that the pin A26 / Boot16 has an impact on the bus width setting of the connected boot device. The RCCR5 has the same bit functions like RCCR2 to RCCR4. Only reset-values differ. For detailed description of function, please see RCCR2-RCCR4. Bit 313029 282726252423 222120191817 16 Name RBA RPM RPWT Bit 15 14 13 12 11 10 987 654321 0 Name RWT RCS RBS RBC RME RSHT Bit Name Reset Configuration Reset Value R/W 31:20 RBA Base Address (default: 0x1FC0 0000) 0x1FC R/W 19:18 RPM Page Mode, Page Size (default: no page mode) 00 R/W 17:16 RPWT The device is not configured for page mode (RPM bits). This means that RPWT and RWT are combined to one counter value for the wait state generation. The wait state counter is set to 64 wait states, that can be reduced in the boot routine to a value that fits to the connected device. 11 R/W 15:12 RWT Normal Mode Wait Time (default: 14 wait cycles) 1110 R/W 11:8 RCS Channel Size (default: 4 Mbyte) 0010 R/W 7 RBS Bus Size (configuration is latched from A26/BOOT16 pin) BOOT16 Pin R/W 6 Wired to zero 0R 5 RBC Byte Control (default: byte enables only active on write access) 0R/W 4 Wired to zero 0R 3 RME Master Enable (default: enabled) 1R/W 2:0 RSHT Setup/Hold Wait Time (default: disabled) 000 R/W |
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