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TMPR3916 Datasheet(PDF) 87 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 87 Page - Toshiba Semiconductor

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Chapter 3 Graphics Display Controller (GDC)
Preliminary
3-8
3.1.4.1
Dot Clock
The dot clock is the reference clock for graphics data output. It is also used to determine the
screen size, for example, of each layer. Use the following formula to select the dot clock:
s)
(
period
display
horizontal
dots)
visible
non
(including
line
per
dots
display
of
number
=
(MHz)
speed
clock
Dot
µ
Note that the internal circuit imposes the following restriction:
dot clock speed (MHz) < ½ SYSCLK.
The dot clock can be provided internally as a derivative of the system clock. The divisor is
defined by DCKPS (see Display Control Register (DCR)) and can be set to 4, 6, 8, …, 24.
Therefore frequencies of 2.5 MHz up to 15 MHz can be reached when using the internal dot clock.
Default setting for DCKPS is 0x4h for a dot clock of 6 MHz.
Alternatively the dot clock may be input via the DOTCLK pin.
3.1.5
Color Palette
In Map mode, each dot can be set for 16 colors using layer C or D and 256 colors using layer A or B.
By using the color palette, any 16 or 256 colors respectively can be selected from among the 65,536
colors. The color palette can be set independently for each layer (A, B, C or D). One of the defined
colors is transparent for layers B, C and D. It must not be used if no background layer is activated.
In Picture mode (layer E), the TMPR3916 can display up to 65,536 colors. The dot data are directly
defined at the frame buffer and therefore no color palette is necessary.
When programming values to CLUT entries the upper 16 bits of the bus represent the color value, the
lower 16 data bits are ignored.
Example: For programming entry #7 in layer A’s color look-up table to a color with a red part
of R = 20, a green pixel G = 23 and a blue one of B = 48, load 0xA5F00000 into
memory location 0x1C05081C.
The following table shows the color palette structure:
Layer
Palette
Name
Number of
Colors
Color Palette
No.
Address
Color Specification
A
CPLTA
256 colors
0
1
:
255
1C05 0800
1C05 0804
:
1C05 0BFC
free defined color 0
free defined color 1
:
free defined color 255
B
CPLTB
255 colors
0
1
:
255
1C05 0C00
1C05 0C04
:
1C05 0FFC
transparent
free defined color 0
:
free defined color 254
C
CPLTC
15 colors
0
1
:
15
1C05 0180
1C05 0184
:
1C05 01BC
transparent
free defined color 0
:
free defined color 14
D
CPLTD
15 colors
0
1
:
15
1C05 01C0
1C05 01C4
:
1C05 01FC
transparent
free defined color 0
:
free defined color 14



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