TMPR3916 datasheet(47/225 Pages) TOSHIBA

47 / 225 page

Chapter 1 The TMPR3916

Preliminary

1-10

1.8

Time-Out-Error Control Unit

This unit is a kind of watchdog unit for the internal CPU-bus.

When a master sends a GBSTART signal, the Time-Out Error Control Unit starts counting cycles. If no

reaction has been detected on the bus, an internal acknowledging GACK is generated after 1024 cycles so

that the bus is free for interaction again.

1.9

Operating Modes of TMPR3916

In Normal Mode, the TX39 core and peripheral circuits operate at maximum frequency.

Halt Mode halts the core operations and reduces power dissipation by stopping the clock in the TX39

core.

To switch to Halt mode, set the Halt bit of the Configuration Register in TX39 core.

In Halt mode, the TX39 core holds the status of the pipeline processing and stops the core operations. The

write buffer does not stop. If data remains in the write buffer when Halt mode is selected, write operations

continue until the write buffer becomes empty. Also SYSCLK does not stop.

The processor is released from HALT mode by using the NMI* signal, RESET* signal or by any kind of

enabled interrupt. The corresponding exception handler is executed after the HALT mode has been released.

Doze Mode halts some TX39 core operations and reduces power dissipation. Unlike Halt mode, only

some clocks in the processor core stop, allowing external bus release requests to be received. Also the

peripheral blocks continue operating normally in Doze mode.

To switch to Doze mode, set the Doze bit of the configuration register in TX39 core.

Standby Mode halts the clock generator PLL circuit operation and reduces power dissipation.

First, set CLKEN pin to low to stop the clock supply. Then, set PLLOFF* pin to low to halt the PLL

circuit operations.

TMPR3916 Datasheet(PDF) 47 Page - Toshiba Semiconductor