TMPR3916 datasheet(60/225 Pages) TOSHIBA

60 / 225 page

Chapter 2 Memory Controller (MC)

Preliminary

2-11

Bit

Name

Function

Reset

Value

R/W

SRM

Self Refresh Mode

This register is used to enter and exit the SDRAM self-refresh mode.

Self-Refresh mode will automatically be entered, by writing this

value of 0 or by conducting a read or write access to the SDRAM

mapped memory region. CEN or ENA may not be deasserted during

self-refresh mode. If self-refresh mode is not utilized, initialize SRM

to 0.

R/W

15:14

RSY

Row Size for channel Y

The RSY, CSY and BSY fields are used to specify the organization of

memory channel Y.

00 = 2 K

01 = 4 K

10 = 8 K

11 = Invalid setting

R/W

13:12

CSY

Column Size for channel Y

Number of Columns

00 = 256

01 = 512

10 = 1 K

11 = 2 K

R/W

BSY

Bank Size for channel Y

Number of Banks

0 = 2 banks

1 = 4 banks

R/W

10:6



Wired to zero

CEN1

Memory Channel Enable Channel Y

1 = Enable address decoding for this channel

0 = Disable address decoding for this channel

This setting enables and disables the address decoding for the

memory channel. A memory channel cannot be accessed, if it is

disabled using this bit and G-Bus transactions within the channel’s

address range will not be answered.

R/W

CEN0

Memory Channel Enable Channel X

1 = Enable address decoding for this channel

0 = Disable address decoding for this channel

This setting enables and disables the address decoding for the

memory channel. A memory channel cannot be accessed, if it is

disabled using this bit and G-Bus transactions within the channel’s

address range will not be answered.

R/W

PRIO

G-Bus Priority Setting

This bit can be used to prioritize the access of one G-Bus. However,

this bit has only a minor impact. In the scenario, the memory

controller is in idle state when both G-Busses simultaneously start a

G-Bus transaction:

1 = G-Bus X will be serviced with priority

0 = G-Bus Y will be serviced with priority

A real prioritization of one G-Bus is not efficient in terms of

performance, since it is not possible to utilize the dual G-Bus

structure under these circumstances. Additionally, the latency of one

G-Bus would become unpredictable.

R/W



Wired to zero

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