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TMPR3916 Datasheet(PDF) 99 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 99 Page - Toshiba Semiconductor |
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99 / 225 page ![]() Chapter 3 Graphics Display Controller (GDC) Preliminary 3-20 Vertical Display End Register (VDER) for layers A/E, B and C Bit 31 2625 1615 0 Name VDE Bit Name Function Reset Value R/W 31:26 Wired to zero 0R 25:16 VDE These specify the vertical display end position using the number of lines, starting from the VSYNC* signal falling edge. Number of display period lines = VDE - VDS 0x0F6 R/W 15:0 Wired to zero 0R Note: The lowest value allowed for VDE is 2hex. Vertical Display End Register (VDERD) for layer D Bit 31 2625 1615 0 Name VDED Bit Name Function Reset Value R/W 31:26 Wired to zero 0R 25:16 VDED These specify the vertical display end position using the number of lines, starting from the VSYNC* signal falling edge. Number of display period lines = VDED – VDSD 0x0F6 R/W 15:0 Wired to zero 0R Note: The lowest value allowed for VDED is 2hex. |
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