TMPR3916 datasheet(95/225 Pages) TOSHIBA

95 / 225 page

Chapter 3 Graphics Display Controller (GDC)

Preliminary

3-16

The specified start address SARx is not the same address as the address on the video bus. The lowest bits

(SS bits) are used internally only (!). The differences are described in figure 12:

SA[10:0]

AC[17:0]

SS[2:0]

SA[10:0]

AC[17:0]

SARx [31:0]

video bus address [31:2]

Used within GDC only

20 19

21 20

logical address

physical address

Figure 3.4.1 Logical Address and Physical Bus Address

Note:

Bit 31 of video bus address is tied to 0.

Memory Width Register A/E, B, C, D (MWRA/E, MWRB, MWRC, MWRD)

Bit

2625

1615

Name



Bit

Name

Function

Reset

Value

R/W

31:26



Wired to zero

25:16

Specifies the line widths of each layer on the frame buffer in one-

word units.

For example, where the line width is 320 dots:

MW = 28hex for layer C and D

MW = 50hex for layer A and B

MW = A0hex for layer E

R/W

15:0



Wired to zero

Horizontal Transfer Number Register (HTN) for layers A/E, B and C

Bit

Name



HTN



Bit

Name

Function

Reset

Value

R/W

31:21



Wired to zero

20:16

HTN

Line Size of Layer A/E, B and C

These specify the number of data transfers for one line. Sets the

number of display dots for one line divided by 32.

R/W

15:0



Wired to zero

Note:

HTN is always rounded to the higher integer value.

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