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TMPR3916 Datasheet(PDF) 84 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 84 Page - Toshiba Semiconductor |
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84 / 225 page ![]() Chapter 3 Graphics Display Controller (GDC) Preliminary 3-5 32 bit frame buffer Line 1 Dot 1 Line 1 Dot 2 Line N Dot 1 Line N Dot 2 To digitalout or VIEWDAC Line 1 Dot n Line N Dot n Figure 3.1.5 Frame Buffer in Case of Layer E The number in MWRx is always rounded to the higher integer. Some display devices do colour calibrations during synchronization periods. That is why the graphics display controller outputs black level as analog output from VIEWDAC while HDISP=0. For digital output this value is stored in register PA (see PORT module) with respect to the output mode (dot or pixel). As a result the PA register has to be initialized with the correct value (reset value: 0x00h). |
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