TMPR3916 datasheet(51/225 Pages) TOSHIBA

51 / 225 page

Chapter 2 Memory Controller (MC)

Preliminary

2-2

2.1

Structure of Memory Controller

TMPR3916 owns two internal busses, the system bus and the video bus. The system bus can be accessed

by the TX39 core and other devices capable of being master on the bus. Additionally, the TMPR3916

provides a second, so called video bus. The video bus is used by the GDC in order to read picture data from

the SDRAM frame buffer. The GDC is the only device on that bus and is not able to write data into SDRAM.

It is only possible to write data into the frame buffer via the system bus. Due to system performance

considerations it is recommended to use SDRAM memory for frame buffer, though it is also possible to

locate the frame buffer in memory devices accessible by the MEMC. For this purpose the TMPR3916

provides a bridge between system and video bus. In order to activate this bridge the SFB bit in Chip

Configuration Register (CCR) needs to be asserted. It has to be assured that the GDC is not accessing

SDRAM mapped memory in this case. In this mode, the system-performance is restricted by the higher

utilization of the system bus and the reduced throughput to the frame buffer memory devices.

The following figure shows the structure of the memory controller:

SDRAM

Controller

internal system-bus

interface

to devices

connected

to the

TMPR3916

MEMC

Video

System

Bus

Bridge

internal video-bus

Figure 2.1.1 Data Flow in Memory Controller

TMPR3916 Datasheet(PDF) 51 Page - Toshiba Semiconductor