TMPR3916 datasheet(58/225 Pages) TOSHIBA

58 / 225 page

Chapter 2 Memory Controller (MC)

Preliminary

2-9

This means for example that the frame-buffer for the video-controller and the program memory

accessed by the MCU should be located in different memory banks. If the condition is not met for two

consecutive addresses, the controller needs to precharge the bank first and it has to wait for the

precharge-to-active-latency before it can start with the access on the second MCU-bus. A memory

throughput gain of up to 40 % can be achieved, if software allows the simultaneous utilization of

several SDRAM banks.

2.5.3

Self-Refresh Mode

The SDRAM controller also offers support for the SDRAM self-refresh-mode. In self-refresh mode,

the connected SDRAM devices maintain data retention without clock-supply and without the

requirement of auto refresh cycles. The self-refresh mode significantly lowers the power consumption

of the connected memory devices.

Self-refresh mode is entered with the assertion of the SRM bit in the DCCR register. The connected

SDRAM channels and the SDRAM controller need to be enabled during this operation.

Upon assertion of this flag, SDRAMC will enter the self-refresh-mode by issuing a self-refresh-entry

command. SDRAMC will remain in self-refresh mode until the deassertion of the SRM flag. The

SDRAMC logic guarantees a minimum time of APL latency cycles in self-refresh mode.

The SRM flag can be cleared in two different ways, by either writing the bit to “0” or by conducting

an access to mapped memory space.

After clearing the SRM flag, the CKE signal is asserted to exit the self-refresh mode. The SDRAM

controller issues NOP commands for the number of cycles specified by the ARL setting. After this, a

regular auto refresh cycle will be conducted to finalize the sequence.

TMPR3916 Datasheet(PDF) 58 Page - Toshiba Semiconductor