TMPR3916 datasheet(48/225 Pages) TOSHIBA

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Chapter 1 The TMPR3916

Preliminary

1-11

1.10 Chip Configuration Register (CCR)

The configuration register is used to configure chip functions concerning more than one module.

Bit

313029

282726

2524

Name



VIEWDAC

SFB

Bit

232221

201918

1716

Name



CANM

CANDIV

Bit

151413

121110

Name



SEIMUX



TOE

BEOW

Bit

765

432

Name

DMA1CC

DMA0CC

Bit

Name

Function

Reset

Value

R/W

31:26



Wired to zero

VIEWDAC

By using this bit it is possible to power down the VIEWDAC.

1 = Enables the VIEWDAC (default)

0 = Disables the VIEWDAC

R/W

SFB

SRAM Frame Buffer:

0 = Display frame is stored in SDRAM

1 = Display frame is stored in SRAM

R/W

23:22



Wired to zero

21:20

CANM

CAN operation mode

00 = Normal mode

X1 = Internal test mode

10 = 2 internal CAN on one TX/RX pair, 1 Transceiver

R/W



Wired to zero

18:16

CANDIV

The CANDIV bits set the clock divider for the CAN modules. The

following table shows possible settings and the corresponding

divider ratios.

000 = Invalid setting

001 = System clock divided by 2

010 = System clock divided by 3 (default)

011 = System clock divided by 4

100 = System clock divided by 5

101 = System clock divided by 6

110 = System clock divided by 7

111 = System clock divided by 8

010

R/W

15:13



Wired to zero

SEIMUX

Determines whether the TXSEI or the UART use pins PIO16 to

PIO29.

0 = The UART uses pins

1 = The TXSEI uses pins

R/W

11:10



Wired to zero

TOE

Time-Out Error Control

The time-out error counter aborts bus transactions with exception

after 1024 cycles, if they are not responded to.

0 = No time-out on internal bus

1 = Abort not responded access on internal bus

R/W

TMPR3916 Datasheet(PDF) 48 Page - Toshiba Semiconductor

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