TMPR3916 datasheet(59/225 Pages) TOSHIBA

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Chapter 2 Memory Controller (MC)

Preliminary

2-10

2.5.4

Configuration Registers

Overview

SDRAMC is configured using a total of four configuration registers. These configuration registers

reside in the SDRAMC configuration area. The configuration registers can be accessed using byte, half-

word and word type accesses. Following, the two memory channels are numbered X (CS0) and Y

(CS1). Each channel can be set up using its own memory configuration. The registers RSX, CSX and

BSX are used to set up the configuration for memory channel X. The registers RSY, CSY and BSY are

used to setup the configuration for memory channel Y.

Control Register (DCCR)

Bit

3130

292827

262524

Name

Bit

2322

212019

181716

Name

RSX

CSX

BSX



ACCD

SRM

Bit

1514

131211

Name

RSY

CSY

BSY



Bit

543

210

Name



CEN

PRIO



ENA

PWR

Bit

Name

Function

Reset

Value

R/W

31:24



Wired to zero

23:22

RSX

Row Size for channel X

The RSX, CSX and BSX fields are used to specify the organization of

memory channel X.

00 = 2 K

01 = 4 K

10 = 8 K

11 = Invalid setting

R/W

21:20

CSX

Column Size for channel X

Number of Columns

00 = 256

01 = 512

10 = 1 K

11 = 2 K

R/W

BSX

Bank Size for channel X

Number of Banks

0 = 2 banks

1 = 4 banks

R/W



Wired to zero

ACCD

Acceleration Disable

Disabling dual G-Bus accelerations significantly lowers system

performance. Therefore, this mode is meant to be used as fault

mode only.

0 = All Accelerations Enabled

1 = Prevents Dual G-Bus Accelerations

R/W

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