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TMPR3916 Datasheet(PDF) 46 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 46 Page - Toshiba Semiconductor |
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46 / 225 page  Chapter 1 The TMPR3916 Preliminary 1-9 1.7 Resets Setting RESET* = Low resets the TMPR3916. RESET* should be held Low for at least 10 cycles of system clock (SYSCLK). Because the RESET* signal is synchronized with the TMPR3916 internal clock, the RESET* signal can be set asynchronously to system clock. At a reset the TMPR3916 will do the following operations: • Pipeline will be stalled, internal states reset. • The valid and lock bits of the TX39 cache will be cleared. During reset period the output signals have the following states: A[31:2] = undefined D[31:0] = undefined BE[3:0]* = “High” RD*, WR* = “High” BURST* = “High” LAST* = “High” SYSCLK = continues outputting clock |
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