HD64F36049 datasheet(350/562 Pages) RENESAS

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Section 17 Serial Communication Interface 3 (SCI3)

Rev. 3.00 Mar. 15, 2006 Page 318 of 526

REJ09B0060-0300

17.4

Operation in Asynchronous Mode

Figure 17.2 shows the general format for asynchronous serial communication. One character (or

frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or

low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are

independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-

buffered structure, so data can be read or written during transmission or reception, enabling

continuous data transfer.

LSB

Start

bit

MSB

Mark state

Stop bit

Transmit/receive data

Serial

data

Parity

bit

1 bit

1 or

2 bits

7 or 8 bits

1 bit,

or none

One unit of transfer data (character or frame)

Figure 17.2 Data Format in Asynchronous Communication

17.4.1

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK3 pin can be selected as the SCI3's serial clock, according to the setting of the COM bit in

SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the

clock frequency should be 16 times the bit rate used.

When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 17.3.

1 character (frame)

0/1

Clock

Serial data

Figure 17.3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)

HD64F36049 Datasheet(PDF) 350 Page - Renesas Technology Corp

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