HD64F36049 datasheet(371/562 Pages) RENESAS

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Section 17 Serial Communication Interface 3 (SCI3)

Rev. 3.00 Mar. 15, 2006 Page 339 of 526

REJ09B0060-0300

17.8

Usage Notes

17.8.1

Break Detection and Processing

When framing error detection is performed, a break can be detected by reading the RxD pin value

directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly

the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if

the FER flag is cleared to 0, it will be set to 1 again.

17.8.2

Mark State and Break Sending

When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are

determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or

send a break during serial data transmission. To maintain the communication line at mark state

until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin

becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission,

first set PCR to 1 and clear PDR to 0, and then clear TE to 0. When TE is cleared to 0, the

transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O

port, and 0 is output from the TxD pin.

17.8.3

Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared

to 0.

HD64F36049 Datasheet(PDF) 371 Page - Renesas Technology Corp