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HD64F36049 Datasheet(PDF) 374 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 374 Page - Renesas Technology Corp |
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374 / 562 page  Section 18 I 2C Bus Interface 2 (IIC2) Rev. 3.00 Mar. 15, 2006 Page 342 of 526 REJ09B0060-0300 SCL ICCR1 Transfer clock generation circuit Address comparator Interrupt generator Interrupt request Bus state decision circuit Arbitration decision circuit Noise canceler Noise canceler Output control Output control Transmission/ reception control circuit ICCR2 ICMR ICSR ICIER ICDRR ICDRS ICDRT I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: SAR SDA Figure 18.1 Block Diagram of I 2C Bus Interface 2 |
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