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HD64F36049 Datasheet(PDF) 376 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 376 Page - Renesas Technology Corp |
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376 / 562 page ![]() Section 18 I 2C Bus Interface 2 (IIC2) Rev. 3.00 Mar. 15, 2006 Page 344 of 526 REJ09B0060-0300 18.3 Register Descriptions The I 2C bus interface 2 has the following registers. • I2C bus control register 1 (ICCR1) • I2C bus control register 2 (ICCR2) • I2C bus mode register (ICMR) • I2C bus interrupt enable register (ICIER) • I2C bus status register (ICSR) • I2C bus slave address register (SAR) • I2C bus transmit data register (ICDRT) • I2C bus receive data register (ICDRR) • I2C bus shift register (ICDRS) 18.3.1 I 2C Bus Control Register 1 (ICCR1) ICCR1 enables or disables the I 2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I 2C Bus Interface Enable 0: This module is halted. (SCL and SDA pins are set to port function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception |
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