HD64F36049 datasheet(551/562 Pages) RENESAS

551 / 562 page

Rev. 3.00 Mar. 15, 2006 Page 519 of 526

REJ09B0060-0300

Item

Page Revision (See Manual for Details)

Amended

Bit

Bit Name Description

STOP

Stop Condition Detection Flag

[Setting conditions]

• In master mode, when a stop

condition is detected after frame

transfer

• In slave mode, when a stop

condition is detected after the

general call address or the first

byte slave address, next to

detection of start condition,

accords with the address set in

SAR

18.3.5 I

2C Bus Status Register

(ICSR)

353

18.7 Usage Note

375

Added

19.3.1 A/D Data Registers A to D

(ADDRA to ADDRD)

380

Amended

…. The temporary register contents are transferred

from the ADDR when the upper byte data is read.

Therefore, byte access to ADDR should be done by

reading the upper byte first then the lower one. Word

access is also possible. ADDR is initialized to H'0000.

Figure 20.1 Block Diagram of

Power-On Reset Circuit and Low-

Voltage Detection Circuit

392

Amended

RES

CRES

Amended

Mode

RES Pin Internal State

Active mode 1

Operates

Active mode 2

Operates (

OSC/64)

Sleep mode 1

Only timers operate

Sleep mode 2

Only timers operate (

OSC/64)

Table 23.2 DC Characteristics (1)

Table 23.11 DC Characteristics

(1)

431,

450

HD64F36049 Datasheet(PDF) 551 Page - Renesas Technology Corp

HD64F36049 Datasheet(HTML) 551 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL