HD64F36049 datasheet(108/562 Pages) RENESAS

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Section 6 Power-Down Modes

Rev. 3.00 Mar. 15, 2006 Page 76 of 526

REJ09B0060-0300

6.1.1

System Control Register 1 (SYSCR1)

SYSCR1 controls the power-down modes, as well as SYSCR2.

Bit

Bit Name

Initial

Value

R/W

Description

SSBY

R/W

Software Standby

This bit selects the mode to transit after the execution

of the SLEEP instruction.

0: Enters sleep mode or subsleep mode.

1: Enters standby mode.

For details, see table 6.2.

STS2

STS1

STS0

R/W

Standby Timer Select 2 to 0

These bits designate the time the CPU and peripheral

modules wait for stable clock operation after exiting

from standby mode, subactive mode, or subsleep

mode to active mode or sleep mode due to an interrupt.

The designation should be made according to the clock

frequency so that the waiting time is at least 6.5 ms.

The relationship between the specified value and the

number of wait states is shown in table 6.1. When an

external clock is to be used, the minimum value (STS2

= STS1 = STS0 =1) is recommended.

NESEL

R/W

Noise Elimination Sampling Frequency Select

The subclock pulse generator generates the watch

clock signal (

W) and the system clock pulse generator

generates the oscillator clock (

OSC). This bit selects the

sampling frequency of the oscillator clock when the

watch clock signal (

W) is sampled. When φOSC = 4 to 20

MHz, clear NESEL to 0.

0: Sampling rate is

OSC/16

1: Sampling rate is

OSC/4



Reserved

These bits are always read as 0.

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