HD64F36049 datasheet(201/562 Pages) RENESAS

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Section 12 Timer V

Rev. 3.00 Mar. 15, 2006 Page 169 of 526

REJ09B0060-0300

12.3.3

Timer Control Register V0 (TCRV0)

TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,

and controls each interrupt request.

Bit

Bit Name

Initial

Value

R/W

Description

CMIEB

R/W

Compare Match Interrupt Enable B

When this bit is set to 1, interrupt request from the

CMFB bit in TCSRV is enabled.

CMIEA

R/W

Compare Match Interrupt Enable A

When this bit is set to 1, interrupt request from the

CMFA bit in TCSRV is enabled.

OVIE

R/W

Timer Overflow Interrupt Enable

When this bit is set to 1, interrupt request from the OVF

bit in TCSRV is enabled.

CCLR1

CCLR0

R/W

Counter Clear 1 and 0

These bits specify the clearing conditions of TCNTV.

00: Clearing is disabled

01: Cleared by compare match A

10: Cleared by compare match B

11: Cleared on the rising edge of the TMRIV pin. The

operation of TCNTV after clearing depends on

TRGE in TCRV1.

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

These bits select clock signals to input to TCNTV and

the counting condition in combination with ICKS0 in

TCRV1.

Refer to table 12.2.

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