| Electronic Components Datasheet Search |
|
HD64F36049 Datasheet(PDF) 220 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F36049 Datasheet(HTML) 220 Page - Renesas Technology Corp |
|
220 / 562 page ![]() Section 13 Timer W Rev. 3.00 Mar. 15, 2006 Page 188 of 526 REJ09B0060-0300 13.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] • When TCNT overflows from H'FFFF to H'0000 [Clearing condition] • Read OVF when OVF=1, then write 0 in OVF 6 to 4 All 1 Reserved These bits are always read as 1. 3 IMFD 0 R/W Input Capture/Compare Match Flag D [Setting conditions] • TCNT=GRD when GRD functions as an output compare register • The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register [Clearing condition] • Read IMFD when IMFD=1, then write 0 in IMFD 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] • TCNT=GRC when GRC functions as an output compare register • The TCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register [Clearing condition] • Read IMFC when IMFC=1, then write 0 in IMFC |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |