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HD64F36049 Datasheet(PDF) 224 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 224 Page - Renesas Technology Corp |
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224 / 562 page ![]() Section 13 Timer W Rev. 3.00 Mar. 15, 2006 Page 192 of 526 REJ09B0060-0300 Bit Bit Name Initial Value R/W Description 1 0 IOC1 IOC0 0 0 R/W R/W I/O Control C1 and C0 When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1x: Input capture to GRC at rising edge and falling edge of the FTIOC pin [Legend] X: Don't care. 13.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR bit in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If the OVIE bit in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed. TCNT is initialized to H'0000. |
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