HD64F36049 datasheet(257/562 Pages) RENESAS

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Section 14 Timer Z

Rev. 3.00 Mar. 15, 2006 Page 225 of 526

REJ09B0060-0300

14.3.5

Timer Output Master Enable Register (TOER)

TOER enables/disables the outputs for channel 0 and channel 1. When

WKP4 is selected for

inputs, if a low level signal is input to

WKP4, the bits in TOER are set to 1 to disable the output

for timer Z.

Bit

Bit Name

Initial

Value

R/W

Description

ED1

R/W

Master Enable D1

0: FTIOD1 pin output is enabled according to the

TPMR, TFCR, and TIORC_1 settings

1: FTIOD1 pin output is disabled regardless of the

TPMR, TFCR, and TIORC_1 settings (FTIOD1 pin is

operated as an I/O port).

EC1

R/W

Master Enable C1

0: FTIOC1 pin output is enabled according to the

TPMR, TFCR, and TIORC_1 settings

1: FTIOC1 pin output is disabled regardless of the

TPMR, TFCR, and TIORC_1 settings (FTIOC1 pin is

operated as an I/O port).

EB1

R/W

Master Enable B1

0: FTIOB1 pin output is enabled according to the

TPMR, TFCR, and TIORA_1 settings

1: FTIOB1 pin output is disabled regardless of the

TPMR, TFCR, and TIORA_1 settings (FTIOB1 pin is

operated as an I/O port).

EA1

R/W

Master Enable A1

0: FTIOA1 pin output is enabled according to the

TPMR, TFCR, and TIORA_1 settings

1: FTIOA1 pin output is disabled regardless of the

TPMR, TFCR, and TIORA_1 settings (FTIOA1 pin is

operated as an I/O port).

ED0

R/W

Master Enable D0

0: FTIOD0 pin output is enabled according to the

TPMR, TFCR, and TIORC_0 settings

1: FTIOD0 pin output is disabled regardless of the

TPMR, TFCR, and TIORC_0 settings (FTIOD0 pin is

operated as an I/O port).

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