SH7101 datasheet(369/486 Pages) RENESAS

369 / 486 page

11. A/D Converter

Rev.2.00 Sep. 27, 2007 Page 335 of 448

REJ09B0394-0200

11.4.3

Single-Cycle Scan Mode

In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (four

channels maximum). Operations are as follows.

1. When the ADST bit in ADCR is set to 1 by a software, MTU, or external trigger input, A/D

conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN11).

2. When A/D conversion for each channel is completed, the result is sequentially transferred to

the A/D data register corresponding to each channel.

3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.

If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.

4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter

enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D

conversion stops and the A/D converter enters the idle state.

11.4.4

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter

samples the analog input when the A/D conversion start delay time (t

D) has passed after the ADST

bit in ADCR is set to 1, then starts conversion. Figure 11.3 shows the A/D conversion timing.

Table 11.3 shows the A/D conversion time.

As indicated in figure 11.3, the A/D conversion time (t

CONV) includes tD and the input sampling time

SPL).

The length of t

D varies depending on the timing of the write access to ADCR. The total

conversion time therefore varies within the ranges indicated in table 11.3.

In scan mode, the values given in table 11.3 apply to the first conversion time. The values given

in table 11.4 apply to the second and subsequent conversions.

SH7101 Datasheet(PDF) 369 Page - Renesas Technology Corp